The NVIDIA Line-up

The idea in one minute#

NVIDIA sells one architecture each generation in many shapes: a flagship data-center GPU, PCIe cards for smaller servers, workstation and gaming cards, a desktop “AI computer”, a robotics module, and the CPUs, DPUs, NICs and switches that tie them together. The same tensor-core design runs through all of them; what changes is how much memory, of what kind, at what power, in what box.

Once you can place a product on two axes, segment (where it runs) and generation (which architecture), the names stop being noise. The figure below is that map. Everything on it was checked on 16 October 2026.

A picture#

How it really works#

One architecture, many products#

Each generation starts as a family of dies. The big one (GH100 for Hopper, and the data-center dies of Blackwell and Rubin) goes into the flagship; smaller dies of the same architecture (AD102 for Ada, GB202 for consumer Blackwell) go into cards. A product is then a die plus a memory system plus a package and power limit:

The memory column decides almost everything about what an AI workload can do on a product. HBM is stacked next to the die and gives terabytes per second; GDDR7 gives about 1.8 TB/s on a card; LPDDR5X gives a lot of capacity at a few hundred GB/s. Topic Hardware for every AI stage puts all of them on one chart.

Decoding the names#

• Code names are scientists: Ampere, Hopper, Ada (Lovelace), Blackwell, Rubin, Feynman. CPUs are named too: Grace, then Vera.
• Die names start with G and the architecture letter: GH100 (Hopper), GB202 (consumer Blackwell), AD102 (Ada). A “100” die is the data-center flagship.
• SXM is NVIDIA’s mezzanine module: the GPU sits on a board with NVLink wiring and up to 1,400 W of power delivery. PCIe cards plug into a normal slot and trade power and NVLink for compatibility. NVL in a card name (H100 NVL) means a pair of PCIe cards bridged with NVLink.
• HGX is the 8-GPU baseboard NVIDIA sells to server makers. DGX is NVIDIA’s own complete system built on it. MGX is the modular reference design server makers use for everything else, including NVL72 racks.
• GH200 / GB200 / GB300 are superchips: an Arm CPU (Grace) and one or two GPUs on one board, joined by NVLink-C2C (lesson 03).
• NVL72 counts the GPUs in one NVLink domain. Beware the counting rule: Rubin’s rack was announced in 2025 as “NVL144”, counting dies, and ships as Vera Rubin NVL72, counting packages. Rubin Ultra’s “NVL576” counts dies again (lesson 05). Always ask what is being counted.
• Ultra marks a mid-generation refresh with more memory and more low-precision math, such as B300 (Blackwell Ultra). It is not a new architecture.

What each segment is for#

• Data-center flagship. Training and serving large models. Bought by the rack.
• Data-center PCIe. Serving smaller models, video and recommendation in ordinary air-cooled servers. The L4 (72 W, 24 GB) is still one of the cheapest ways to serve a small model in a cloud.
• Workstation. Development, fine-tuning and private inference on one desk. The 96 GB RTX PRO 6000 is the largest-memory card NVIDIA sells.
• PC and desktop AI. GeForce for gaming and hobby work; DGX Spark puts 128 GB of unified memory in a small box so a 200B-parameter model at 4 bits can at least run locally.
• Edge. Jetson modules run perception and, now, language models inside robots and machines, on a power budget measured in tens of watts.
• CPUs, DPUs, networking. Half of a modern cluster’s design. Grace and Vera feed the GPUs; ConnectX NICs and BlueField DPUs connect them; Quantum (InfiniBand) and Spectrum (Ethernet) switches join racks (lesson 06).

Code#

A small product table and a question every buyer asks: which NVIDIA parts can hold this model, and how fast can one user decode on each? The decode bound is the lesson from 2.c: each new token reads every weight once, so tokens per second cannot exceed bandwidth divided by model size.

// lineup.go — which NVIDIA parts can hold a model, and the decode ceiling on each.
package main

import "fmt"

type Part struct {
	Name, Segment string
	MemGB         float64 // memory the GPU can address at full speed
	BandwidthGBs  float64
	Watts         float64
}

func main() {
	parts := []Part{
		{"L4", "dc-pcie", 24, 300, 72},
		{"RTX 5090", "pc", 32, 1792, 575},
		{"RTX PRO 6000", "workstation", 96, 1792, 600},
		{"DGX Spark (GB10)", "desktop", 128, 273, 240},
		{"Jetson AGX Thor", "edge", 128, 273, 130},
		{"H100 SXM", "dc", 80, 3350, 700},
		{"H200", "dc", 141, 4800, 700},
		{"B200", "dc", 180, 8000, 1000},
		{"B300", "dc", 288, 8000, 1400},
		{"Rubin", "dc", 288, 22000, 2000},
	}
	models := []struct {
		Name          string
		Params, Bytes float64 // billions of parameters, bytes per parameter
	}{
		{"Llama-class 8B, BF16", 8, 2},
		{"70B, FP8", 70, 1},
		{"70B, 4-bit", 70, 0.5},
		{"235B MoE, 4-bit", 235, 0.5},
	}
	for _, m := range models {
		size := m.Params * m.Bytes
		fmt.Printf("\n%s: %.0f GB of weights\n", m.Name, size)
		for _, p := range parts {
			// leave 20% for activations, KV cache and the runtime
			if size > p.MemGB*0.8 {
				continue
			}
			tps := p.BandwidthGBs / size
			fmt.Printf("  %-18s %-12s ≤ %5.0f tok/s per user   %5.2f tok/s per watt\n",
				p.Name, p.Segment, tps, tps/p.Watts)
		}
	}
}

Run it and notice three things. A 70B model at FP8 (70 GB) does not fit an 80 GB H100 once you leave room for the KV cache, yet it fits a 96 GB workstation card, at a quarter of an H200’s speed. The desktop and edge parts hold a 70B model at 4 bits but decode it at about 8 tokens a second: capacity and bandwidth are different products. And the little 72 W L4 is competitive in tokens per watt on the 8B model, which is why it is still sold. (For a mixture-of-experts model only the active experts are read per token, so its real decode bound is higher than the last block shows.)

Remember this#

• Place every product on two axes: segment and generation. The architecture is shared; memory, power and packaging differ.
• The memory system (HBM, GDDR7, LPDDR5X) decides what a product can do for AI.
• SXM, PCIe, HGX, DGX, MGX and superchip name the shape, not the chip.
• When a name contains a number of GPUs, check whether it counts packages or dies.

Try it#

1. Run lineup.go. Add the GB300’s 288 GB and a DGX Station (288 GB of HBM at 8 TB/s). Which models newly fit?
2. Change the 20% headroom to 40% (long-context serving needs a large KV cache). Which parts drop out for the 70B FP8 model?
3. Find the current data sheet for one part in the table and correct any number that has moved.

Check yourself#

1. What is the difference between HGX, DGX and MGX?
2. Why does DGX Spark hold a bigger model than an RTX 5090 but decode it more slowly?
3. What does “NVL72” count, and why must you check the counting rule for Rubin Ultra?

Sources#

• NVIDIA data center GPUs and product data sheets (H100, H200, B200, GB200 NVL72, GB300 NVL72)
• NVIDIA RTX PRO 6000 Blackwell
• NVIDIA DGX Spark and Jetson AGX Thor
• NVIDIA Rubin platform announcement (CES 2026)